Field
The present disclosure relates generally to a layout construction, and more particularly, to a layout construction for addressing electromigration (EM) in a complementary metal oxide semiconductor (CMOS) device.
Background
EM is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. EM can cause the eventual loss of connections or failure of an integrated circuit (IC), and therefore decreases the reliability of ICs. Accordingly, methods of laying out CMOS devices for addressing EM are needed. Further, CMOS devices with layout constructions for addressing EM are needed.